The present invention relates to a driving circuit and an EL display device, and in particular to a driving circuit suitable for a high voltage drive of a capacitive load and an EL display device using this driving circuit.
Capacitive loads such as EL panels, piezo-electric elements, and similar driven devices are typically with a high voltage, and a high withstand voltage is required for the driving circuit therefor. Further the driving circuit for the capacitive load should be provided in general with a source side switch for charging the load and a sink side switch for discharging the load, which has been once charged.
For the driving circuit for a capacitive matrix load such as an EL panel, it is desired to integrate a number of output channels, in carrying out this integration, it is an important problem to reduce the electric power consumption in the driving circuit. An example of such a driving circuit, in which a thyristor is used, is disclosed in JP-A-60-208119, with an intention of reducing the electric power consumption and increasing the load current driving power. This is shown in FIG. 6.
In FIG. 6 there are disposed a thyristor 8, whose anode and cathode are connected with a power source terminal 201 and an output terminal 3, respectively; a diode 9, whose cathode and anode are connected with the cathode-gate of the thyristor 8 and the cathode thereof respectively; an NPN transistor 11, whose collector and emitter are connected with the anode-gate of the thyristor 8 and a power source terminal 202 through a resistor 12, respectively; and an NPN transistor 10, whose collector and emitter are connected with the cathode-gate of the thyristor 8 and the power source terminal 202, respectively, which constitute an output section. The bases of the NPN transistors 10 and 11 are connected with the drains of PMOS transistors 72 and 71, respectively, within a buffer circuit 207 driving the output section described above, responding to signals coming from a logic circuit 206. Further the sources of the PMOS transistors 71 and 72 are connected with a low voltage power source terminal 204. The logic circuit 206 controls the buffer circuit 207, responding to the input signal through an input terminal 205 and it can be constructed by a shift register and a latch circuit, or similar circuitry in the case w ere the output section is constructed by integrating a number of channels. The drive of a capacitive load connected with the output terminal 3 will be explained below.
Now it is supposed that the power source terminal 201 is biased by a positive high voltage V.sub.HP ground potential GND. In the case where the capacitive load 13 is charged by the positive high voltage V.sub.HP, the thyristor 8 may be switched-on by turning the NPN transistor 10 to the OFF state. The ON drive of the thyristor 8 is effected by drawing-out the gate driving current through the anode-gate of the thyristor 8 by turning-on the PMOS transistor 71 within the buffer circuit 207 to turn-on the NPN transistor 11. This gate driving current is brought about through the power source terminal 201 biased by the high voltage V.sub.HP.
Next, in the case where the capacitive load 13, which has been once charged by the high voltage V.sub.HP, is discharged, the thyristor 8 is turned to the OFF state by turning-on the NPN transistor 10. The NPN transistor 10 is turned-on by turning-on the PMOS transistor 72 within the buffer circuit 207 to supply the base current through the low voltage power source terminal 204. Since, in the circuit indicated in FIG. 6, the discharging current from the capacitive load 13 flows through a diode 9 to the NPN transistor 10, the circuit between the cathode-gate and the cathode of the thyristor 8 is reverse-biased and further the cathode-gate of the thyristor 8 is biased towards the GND side by the NPN transistor 10. In this way it is possible to prevent erroneous operations of the thyristor 8.
A case where the driving circuit indicated in FIG. 6 is applied to the drive of the EL panel scan side electrodes will be explained below.
In the EL panel there are disposed scan side electrodes, to which a high voltage is applied sequentially and selectively, and data side electrodes, to which a relatively low voltage is applied in synchronism therewith, responding to lightening and non-lightening data, which are crossed with each other, an EL layer being formed between the two kinds of electrodes. A part put between a scan side electrode and a data side electrode constitutes a pixel, which is equivalent to a capacitive load. The light emission starting voltage is as high as about 200 (V) as disclosed in JP-A-60-97394. Since the EL panel has the polarization effect, it can be driven by an AC voltage. That is, when an EL element is discharged to emit light after having been once charged with a certain voltage polarity, polarization is produced in the direction, where the voltage polarity applied previously is canceled. Therefore, when it is again charged by applying a voltage of same polarity thereto and made emit light, the brightness of the emitted light is reduced. Consequently, in the case where an EL element, which has been once made emit light, should be made again emit light, it is necessary to apply a voltage having a polarity, which is opposite to preceding one, thereto. As examples describing such a method for driving an EL panel, there are known literatures, e.g. "Bidirectional Push-Pull Symmetrical Driving Method For A TF-EL Display (in Japanese)" Sharp Technical Report, Vol. 38, 1987, etc.
FIG. 7 shows an example, in which a number of channels of the driving circuits indicated in FIG. 6 are integrated and applied to the drive of the scan side electrodes in an EL panel as described above.
In FIG. 7, thyristors 81, 82, . . . , NPN transistors 101, 102, . . . , 111, 112, . . . , resistors 121, 122, . . . , etc. corresponding to the thyristor 8, the NPN transistor 10, 11 and the resistor 12 indicated in FIG. 6 are disposed for every channel, power source terminals 201 and 202 being used in common. An output terminal 31, 32, . . . for each of the channels corresponds to one line of the scan side electrodes. Further each of C1, C2, etc. corresponds to one line of the data side electrodes and each of the capacitive loads 311, 312, etc. connected between the two kinds of electrodes corresponds to one pixel. Hereinbelow the capacitive loads 311, 312, etc. are called pixels 311, 312, etc.
Since the circuit for driving the scan side electrodes applies both positive and negative polarity high voltage signals to the data side electrodes, as described also in the example of literature stated above, the power source lines therefor, i.e. power source terminals 201, 202, 204, etc. in FIG. 7, are floating and control signals are inputted through photo-couplers, etc. Further the potential at the low voltage power source terminal 204 is kept always at about 5 (V) with respect to the potential at the power source terminal 202.
At first the case where charging of the pixel and light emission are effected by applying a positive high voltage V.sub.HP to the scan side electrode 31 will be described.
Now it is supposed that the power source terminal 201 is biased by the positive high voltage V.sub.HP and the power source terminal 202 by 0 (V) and that the data side electrode C1 is biased by 0 (V) and C2 by a voltage V.sub.D. Denoting the light emission starting voltage of the EL pixel by V.sub.T, relationships expressed by V.sub.HP &gt;V.sub.T and V.sub.HP -V.sub.D &lt;V.sub.T are supposed to be valid. In this state the positive high voltage V.sub.HP is sent to the scan side electrode 31 by turning-on only the thyristor 81. At this time the voltage between the two terminals of the pixel 311 is V.sub.HP. Since this voltage exceeds the light emission starting voltage V.sub.T, the pixel 311 emits light. On the other hand, since the voltage between the two terminals of the pixel 312 is V.sub.HP -V.sub.D, and since this voltage does not reach the light emission starting voltage V.sub.T, the pixel 312 does not emit light. In this way it is possible to decide emission and non-emission of light by the pixels on the selected scan side electrode (in the case described above scan side electrode 31) by using a relatively low voltage V.sub.D applied to the data side electrode.
After charging of the pixel and emission (or non-emission) of light have been effected by the positive high voltage V.sub.HP, the pixel is discharged to prepare for the succeeding driving timing. The discharge of the pixels on the scan side electrode 31 can be effected by turning-on the NPN transistor 101. By the procedure described above the drive of the scan side electrode 31 is terminated and the succeeding scan side electrode 32 is selected and driven. When it is terminated in this way to select and drive all the scan side electrodes, the procedure returns to the selection of the first scan side electrode 31. However, because of the polarization effect of the EL pixel, it is necessary to apply at this time a voltage having a polarity opposite to that used at the last time. Therefore, at this time, the power source terminal 202 is biased by a negative high voltage V.sub.HN and the power source terminal 201 by 0 (V) so that only the NPN transistor 101 is turned-on to send the negative high voltage V.sub.HN to the scan side electrode 31. Here V.sub.HN is supposed to satisfy relationships expressed by .vertline.V.sub.HN .vertline.&lt;V.sub.T and .vertline.V.sub.HN .vertline.+V.sub.D &gt;V.sub.T.
Now, if it is supposed that the data side electrode C1 is biased by 0 (V) and C2 by the voltage V.sub.D, since the voltage between the two terminals of the pixel 311 is .vertline.V.sub.HN .vertline., the voltage does not reach the light emission starting voltage V.sub.T and therefore no light is emitted. On the other hand, for the pixel 312, since the voltage between the two terminals thereof is .vertline.V.sub.HV .vertline.+V.sub.D, the voltage applied thereto exceeds the light emission starting voltage V.sub.T and light is emitted.
After charging of the pixel and emission (or non-emission) of light by this negative high voltage V.sub.HN, the thyristor 81 are turned-on to discharge the pixels on the scan side electrode 31 and the procedure proceeds to the selection of the succeeding scan side electrode 32.
In the example of literature stated above the method, by which the polarity of the applied voltage is inverted for every scanning electrode, is used. In any case, viewed from a certain scanning electrode, the polarity of the voltage is inverted for every time to select and drive the pixel. For this reason the voltages applied to the power source terminal 201 and 202 are switched over by an external switching element.
In the prior art circuit the ON driving current for the thyristor 8, i.e. the gate driving current, flows from the power source terminal 201 through the PNP transistor 11 to the power source terminal 202. At this time, since the power source terminal 201 is at a potential higher than that at the power source terminal 202, this gives rise to a problem that electric power consumption due to the gate driving current is great. Regarding this point it is possible also to intend to reduce effectively the gate driving current of the thyristor 8 to decrease the electric power consumption by disposing a one-shot circuit within the logic circuit 206 and by pulse-driving a PMOS transistor 71 and an NPN transistor 11. However this causes complication of the logic circuit, which in turn gives rise to increase in the chip area. Further, in the case of this pulse-driving, after the thyristor 8 has been once turned-on, since there exists no more gate current, when the current flowing through the thyristor 8, i.e. pixel charging current, decreases below the holding current of the thyristor 8, the thyristor 8 is turned-off, which gives rise also to a problem that the charging voltage of the pixel is lowered. In addition, in the case where a number of channels are integrated as indicated in FIG. 7, by the construction of the prior art circuit, since a high potential difference is produced between the power source terminals 201 and 202, if short-circuit takes place between different output terminals at the exterior, short-circuit current flows through the path of power source terminal 201--source side switching element (e.g. thyristor 81) --sink side switching element (e.g. NPN transistor 102)--power source terminal 202 between different channels. That is, this can take place e.g. in the case where the scan side electrode 31 is selected, to which the high voltage V.sub.HP is applied and the other scan side electrodes 32, . . . are at 0V, so that the NPN transistors 102, . . . , etc. are turned-on. In order to limit the short-circuit current stated above and to prevent the destruction of the integrated circuit, the source side or the sink side switching element should have the current limiting function. In the examples indicated in FIGS. 6 and 7, the NPN transistor used on the sink side carries out this function.
As explained above, in the prior art circuit, in some cases the load driving current power should be limited. This gives rise to a problem, when it is applied to an EL display device, where required current driving power increases with increasing size of the panel.